By Emilia Käsper, Peter Schwabe (auth.), Christophe Clavier, Kris Gaj (eds.)
This e-book constitutes the refereed court cases of the eleventh foreign Workshop on Cryptographic and Embedded structures, CHES 2009, held in Lausanne, Switzerland in the course of September 6-9, 2009.
The e-book comprises three invited talks and 29 revised complete papers that have been rigorously reviewed and chosen from 148 submissions. The papers are geared up in topical sections on software program implementations, aspect channel research of mystery key cryptosystems, part channel research of public key cryptosystems, part channel and fault research countermeasures, pairing-based cryptography, new ciphers and effective implementations, TRNGs and gadget id, trojans and depended on ICs, theoretical elements, and fault analysis.
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Extra info for Cryptographic Hardware and Embedded Systems - CHES 2009: 11th International Workshop Lausanne, Switzerland, September 6-9, 2009 Proceedings
Sample text
Despite this issue, the Rijndael S-box’ excellent cryptographic properties have led to its inclusion in other ciphers, including the LEX stream cipher [5], the Fugue hash function [7] and the Camellia block cipher [10]. C. Clavier and K. ): CHES 2009, LNCS 5747, pp. 18–32, 2009. c International Association for Cryptologic Research 2009 Accelerating AES with Vector Permute Instructions 19 Several processors — including the VIA C3 and higher, the AMD Geode LX and the forthcoming Intel “Sandy Bridge” and AMD “Bulldozer” cores — support hardware acceleration of Rijndael.
4964, pp. 187–202. Springer, Heidelberg (2008) 23. : How far can we go on the x64 processors? B. ) FSE 2006. LNCS, vol. 4047, pp. 341–358. pdf 24. : On the power of bitslice implementation on Intel Core2 processor. , Verbauwhede, I. ) CHES 2007. LNCS, vol. 4727, pp. 121–134. 1007/978-3-540-74735-2_9 25. pdf 26. : The security and performance of the Galois/Counter Mode (GCM) of operation. , Viswanathan, K. ) INDOCRYPT 2004. LNCS, vol. 3348, pp. 343–355. Springer, Heidelberg (2004) 27. : Advances on access-driven cache attacks on AES.
J vj PSHUFB From a source (x0 , x1 , . . , x15 ), and destination register (y0 , y1 , . . , y15 ), the result at position i is xyi mod 32 . Here x16 through x31 are taken to be 0. PMULHRSW This gives the rounded higher word of the product of two signed words in each of 8 positions. ] The source register xmm (j) can usually be replaced by a 16-byte-aligned memory region. The interested reader is referred to Intel’s manual for further information on optimizing for the x86-64 architecture [26].